Autonomous wireless state radios and sensor/actuator systems may be characterised by having no local user interfaces and are often required to be Always-ON. Always-ON in this context is characterised by long periods of standby (more than 99% of the time) with short bursts of activity, during which, for example, a transmission is made and/or measurements are taken or actuators operated.
During standby, certain system functions have to be maintained. This critically involves, for example, scheduling of the next transmission and maintaining state information, but may also include continuous sensing.
Advances in low power CMOS process technology have been driven by mobile computing applications and such systems directly benefit from improved fabrication technologies. In many cases the use of advanced CMOS technology is necessary in order to support the active function of a CMOS system within the power limitations of single battery cells or energy harvesters.
Advances in CMOS transistor technology have reduced the power required for both logic operations as well as the active power consumption of the analogue parts of a radio or sensor fabricated using such technology. FIG. 1 illustrates the power consumed by a CMOS circuit in standby and transmission modes for transistors fabricated using conventional (older) and advanced (newer) CMOS transistor technology. FIG. 1 indicates that the peak power consumption during logic operations in the ON-state is reduced in circuits fabricated using advanced CMOS transistor technology when compared to conventional CMOS fabrication technology. FIG. 1 also shows that the static power consumption of CMOS circuits using advanced CMOS transistor fabrication technology in the standby or OFF-state is higher than in the case of CMOS circuits fabricated using conventional CMOS fabrication technology, as this is dominated by leakage power which is typically higher when using advanced CMOS transistor fabrication technology.
We distinguish different operating states of the system:                Active: Key processing blocks are powered-up and operate at high clock frequency. Typically active power consumption dominates.        Sleep: Most circuitry powered off, with a small subset of “Always-ON” circuitry clocked at low clock frequency and powered with reduced supply voltage, providing a keep-alive function and scheduling active operation. Typically static power consumption dominates over the active switching power in this case.        
Due to higher static power consumption, the average power consumption can be dominated by the leakage power consumed by circuits that remain powered during the sleep. This is seen by the higher average power consumption in FIG. 1 for circuits fabricated using advanced CMOS technology compared to those fabricated using conventional CMOS technology.
CMOS circuits for certain types of device can be split into blocks of Always-ON circuitry and blocks which are powered only during Active operation. The Always-ON logic circuitry represents a fraction of the total standard cell area, for which low leakage is the single most important requirement. These blocks conventionally use devices with a high threshold voltage (HVT), and are responsible for the higher power consumption in the sleep state as seen in FIG. 1.
The blocks powered up during Active operation are usually optimised for speed and low dynamic power and contain higher performance devices with lower threshold voltage (LVT).
An inverter is a representative of a functional building block implementing a logic function. It is widely known in the art of circuit design that an inverter comprises NMOS and PMOS transistors connected in series with tied inputs. There are two distinct leakage mechanisms at work in an inverter:                Transistors in the OFF state (VGS=0, VDS=VDD):         The drain off-current divides into sub-threshold current to the source, bulk leakage current and gate leakage current.        Transistors in the ON state (VGS=VDD, VDS=0):         In this case leakage current is due to tunnelling currents between the channel and the gate.        
In addition to the above, FIG. 2 shows the variation of drain leakage current Id(off) and bulk leakage current Ib(HVT) in the OFF-state of an HVT transistor exemplified by an NMOS transistor with a gate length L of 0.09 μm. The bulk OFF-state current Ib(LVT) of a corresponding LVT NMOS transistor is also shown in the figure for comparison. It is clear from FIG. 2 that the bulk leakage current in the HVT transistors must be reduced in order to achieve a further reduction of the total device leakage current.
HVT transistors fabricated using advanced CMOS fabrication technology typically use high dose pocket and extension implants with the aim of reducing short channel effects and sub-threshold leakage currents. However, the resulting highly doped, abrupt junctions cause significant junction leakage. A further reduction in the sub-threshold leakage currents can be achieved by increasing the gate length L above the minimum gate length Lmin defined for the advanced CMOS fabrication technology being used. However, the junction leakage of the drain junction must be reduced in order to allow a reduction of the overall leakage. Finally, ON-state gate leakage sets a total leakage current floor depending on the supply voltage.
There therefore remains a need of further reducing the total leakage current and supply voltage in CMOS devices used in Always-ON circuits and facilitating the use of such devices in logic standard cells without adding complexities to current state of the art CMOS fabrication technology.